Efforts of the semiconductor fabricating industry to produce continuing improvements in miniaturization and packing densities has seen improvements and new challenges to the semiconductor fabricating process. One example semiconductor process experiencing tremendous improvements in miniaturization and packing densities is ultra-violet lithography. Making use of the pattern transfer ability of photoresist materials formed into patterns through lithography exposure and developing, semiconductor pitch sizes have fallen steadily. Today lithography techniques patterning with 193 nanometer (nm) Argon Fluoride (ArF) photoresists are enabling process technologies to reach pitch structures as small as 43 nm and 32 nm NAND. The “pitch” of a semiconductor structure is a common measurement of the technological generation of a semiconductor chip. It refers to a hypothetical distance between structures in a semiconductor substrate.
With the use of ArF photoresist in ultra violet lithography and pitch sizes dropping below 100 nm, the phenomenon of line-edge roughness is now a serious problem. As illustrated in FIGS. 1A, 1B, and 2, the ideal, smooth lines seen in the hypothetical resist lines of FIG. 1A are distorted by irregularities seen in FIG. 1B. While not drawn to scale and exaggerated for clarity, the irregularities in FIG. 1B serve to illustrate how imperfections and defects in the photoresist may produce ripples and uneven line edges in trenches and other structures formed during the plasma etching process, as illustrated in FIG. 2. What would have been a tolerable amount of line-edge roughness in larger pitch structures produces unacceptable defects in tighter pitch structures below 100 nm as discussed below. FIG. 2, a cross-section of FIG. 1B, also not drawn to scale and exaggerated, illustrates the irregularities 202 of the photoresist 204 transferring to the line edges 206 of trenches and other structures etched into the underlying layers, producing undesirable irregularities in the resulting line edges 206. Line edge roughness in the x-y direction as shown in FIG. 1B may translate straight downward and manifest itself as variations in line width as illustrated in FIG. 2. For example, line 208 is narrower than the other lines at the cross-section point while line 210 is wider than the other lines at the cross-section point. This difference in line width at the cross-section point is caused by the line ripples illustrated in FIG. 1B, translated straight downward. As discussed further below, these resulting irregularities in semiconductor structures are measured according to an average line-edge roughness and/or line-width roughness.
The use of ArF photoresist in ultra violet lithography exacerbates the problem of line-edge roughness. Ultra violet photoresist is especially sensitive to the plasma etching applied to the underlying semiconductor substrate structures. Ultra violet photoresist's sensitivity to plasma causes distortions in the resist line as the etching process continues, and therefore, forming the line edges of trenches and other structures underneath the photoresist with distortions transferred from the photoresist.
Photoresist is not a uniform material; it contains “lumps” of polymer aggregates that have become a concern especially now that resist lines are fine enough that atomic effects may be seen. When atomic effects begin to play a part in the quality of line edges, the clusters of polymers that may form in the photoresist now lead to deformities that may be seen in tight line edges. Therefore, when a line is developed in the photoresist, little ripples in the line edge begin to form due to the hard and soft places in the photoresist. Rather than a homogenous material, photoresist is an aggregate of multiple materials, and as the photoresist is etched, the plasma (which is a mixture of ions and neutrals) hitting the wafer causes chemical reactions and raises the temperature of the photoresist and the wafer. The softer areas of the photoresist are more easily etched away, leaving behind rough and potentially uneven harder areas of the photoresist. As the etching process continues, the polymer formations in the aggregate photoresist are revealed. The plasma etching process further distorts the photoresist by heating it and changing its chemical components, causing a stress change in the resist. The lines patterned in the photoresist react to that stress change resulting in a buckling of the photoresist, with all of these affects becoming more visible and problematic as pitch sizes shrink with each technological generation. In other words, while these effects were always present in previous generations, pitch sizes below 100 nm are more sensitive to these photoresist irregularities.
With 193 nm ArF photoresist, lines are developed extremely close together, requiring low wavelength, high frequency light (193 nm). To ensure that such a short wavelength gets into the resist to pattern it, the resist must be made very thin. However, the photoresist thickness is the mask for the etching process. A thin resist is more easily patterned, but is also more vulnerable to the damaging effects of etching. Further, the etching process itself reduces the photoresist mask during etching. Eventually as aggregates are exposed along the resist line edge, a ripple on the line edge of the photoresist may be passed on to the underlying films during etching.
This line edge rippling can result in breaks in the copper lines eventually formed in the etched trenches of 43 nm NAND. When this technology is applied to structures as small as 43 nm NAND, the present line-edge roughness is now visible as ripples in the line edges. The end result is devices that don't work. In other words, any problems with roughness that had existed in past generations have been greatly magnified by going down to 43 nm NAND. The increased line-edge roughness results in whole chips that don't work because of roughness causing crude defects such as shorts and breaks in the copper lines formed in the trenches etched through the patterned resist lines.
Another associated effect with line-edge roughness that is also increasingly seen in 43 nm NAND fabrication is line wiggling. As seen in FIG. 3, the lines have moved into a wiggling pattern as opposed to the expected straight lines of FIG. 1A. A physical stress has produced this “wiggling” in the etched lines or trenches. It isn't just that there are polymer aggregates that are revealed at the edge as seen in line-edge roughness—here there's some added stress. There is some inherent stress in the photoresist, but as described above, the polymer aggregates change when they are heated up, becoming different from the surrounding material. As the underlying layers or films are etched through the photoresist pattern, material from the etching is implanted into the underlying films from the etching process. Further, with each etch, a different film under the film currently being etched is revealed. Each film revealed has different stresses and as they are each etched their stresses are mismatched with the layer above, each mismatched stress contributing to the characteristic wiggle as seen in FIG. 3.
Until recently, the standard approach (e.g., adding pattern transfer layers and reducing etching power) to reduce line-edge roughness was to varying degrees at least adequate for pitches greater than 100 nm. However, with pitches smaller than 100 nm, even low levels of line-edge roughness are producing unacceptable results and new solutions are needed.